Tuesday, 28 March 2017, from 2pm to 4pm
Room : Ada Lovelace (Inria Bordeaux 3rd floor)
Programme
- Xeon Phi Architecture Overview and roadmap - Asma Farjallah , HPC Application Engineer (Intel) & Alexandre Chauvin , HPC Account Executive (Intel)
- Evaluation and Usability of the Cache Aware Roofline Model on PlaFRIM Knight Landings - Nicolas Denoyelle (TADaaM)
- Evaluating the impact of Intel KNL memory settings on performance through case studies - Ian Masliah (HiePACS)
- Exploiting multi-level parallelism on Intel KNL - Terry Cojean (STORM)
- Exchanges
